Studiebog
    Three-Dimensional Integrated Circuit Design

    Three-Dimensional Integrated Circuit Design

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    Bog E-bog
    • Format
    • Bog, paperback
    • Engelsk

    Beskrivelse

    Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires

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  • Vægt1590 g
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    10 cm
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    19,1 cm
    23,4 cm

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    Vertical integration Liquid cooling System-in-Package Thermal coupling Emerging technologies Multigrid Method On-chip Interconnects 3-D cache memory 3-D clock tree synthesis 25-D integration 3-D power distribution networks 3-D IC thermal models 3-D NoC performance models 3-D routing 3-D ICs 3-D placement 3-D microprocessor 3-D NoC power models 3-D floorplanning 3-D global clock distribution networks 3-D net timing optimization 3-D networks-on-chip 3-D packaging 3-D global clock networks 3-D H-trees 3-D power delivery AC Coupling Contactless intertier communication Contactless 3-D circuits Decoupling capacitance Crosstalk Noise Compact TSV models Dynamic Thermal Management Clock skew modeling Clock skew variations FEM method Heat transfer in ICs Die-to-die variations Interposers Interposer cost modeling Elmore Delay Inductive links Interconnect models Force directed placement Fixed outline floorplanning Monolithic or sequential integration Manhattan plane Multilevel power delivery in 3-D ICs Multi-TSV 3-D nets Polylithic or parallel integration On-chip inductors Rent's rule Prebond testable clock trees Sequence pair technique Skitter Redistribution layers Heterogeneous 3-D ICs Substrate resistivity Substrate noise models Substrate noise reduction Manhattan sphere Thermal-driven placement Thermal TSVs TSV cost modeling TSV power distribution paths TSV tapering System-on-package Timing-driven multi-TSV placement Interposer yield Vertical Interconnects Within-die variations Tier partitioning Timing-driven TSV placement TSV to substrate coupling TSV processing steps TSV yield Thermal-driven floorplanning Thermal wires Power supply noise in 3-D circuits Manhattan Distance On-chip heating circuits Panel interposers Multipin 3-D nets Process variability in 3-D circuits TSV capacitance TSV fault tolerance TSV modeling TSV resistance Wire sizing for power integrity Thermal hot spots Through silicon vias (TSVs) TSV thermal models three-dimensional integration TSV coupling TSV inductance Wafer interposers

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